A dual inline memory module (DIMM) includes a specified number of memory chips and I/O lanes scaling with an X86 processor memory interface. Currently, the bus width for DDR1, DDR2, DDR3, and SDR is 64 bits. To supply the required 64 bit bus, typical DIMMs for desktop PCs are 8×8 memory chips.
FIG. 4 shows a prior art dual inline memory module (DIMM) comprising 8×8 memory chips M1-M8. The first seven memory chips M1-M7 may be used for data storage and the last memory chip M8 may be used for ECC bit storage. This conventional DIMM is required to have a 72 bit bus width of the DQ bus which includes write data wD, read data rD, and ECC bit signals from/to a memory controller MC. For example, DDR3-DRAM on a conventional DIMM have a single bidirectional bus for rD and wD. The CA bus transmitting command and address signals CA from the memory controller MC to the DIMM comprises (in this example) 20 lines. Since a normal connector C of the DIMM has a maximum pin count of 240, a differential signalling which a 72×2=144 bit DQ bus 120×2=240 CA bus cannot be realized with the conventional DIMM. One problem for the pin count is that you need a ratio of 2:1:1 signal to power to ground, so one needs to double the pin count compared to just counting the signal pins.
Increasingly, applications are requiring different bus width. Normal servers use 72 bit wide busses to get additional 8 bits for error correction codes (ECC). In addition, high end servers need to combine 2/4 channels to get a 144/288 bit wide data bus to implement more sophisticated error correction algorithms (for example, a chip kill to repair a complete single chip failure). Furthermore, game consoles, mobile applications, network applications, graphic applications and set top boxes can, for example, utilize smaller bus width as they do not need so much memory capacity.
Since high end servers need to combine 2/4 channels to get a 144/288 bit wide data bus to be able to implement a more sophisticated error connection algorithm (e.g. a chip kill to repair a complete single bit failure), there arises the problem that the processor (processor cache) needs a specific amount of memory per need access and that a combination of several channels gives back more data bits per read command that the processor cannot utilize.
Furthermore, modern memory systems increasingly include memory chips (DRAMs) with a single CA bus that is 20 bit wide, so it is difficult to change the bus width for the DIMM. Consequently, the standard 64 bit approach is not practical for different applications, lacking adaptability. In addition, data, command, and address signals of future memory generations will be transmitted as differential signal pairs. This has the disadvantage of necessitating double pin count, (i.e., 128 pins for a 64 bit bus). This is not possible with present DIMMs. Changing to a 32 bit bus with double speed would hold the DQ pin count constant, but the command and address signals cannot be supplied fast enough to all chips in the conventional method. This means that also the command and address signals require a point-to-point signal connection, which adds pin count at the connector of the DIMM for additional DRAM chips. In view of the above, use of a conventional DIMM having a 240 pin connector for providing, e.g., four data lanes plus 1 ECC lane will be difficult to realize. Consequently, it would be desirable to decrease the pin number of a memory module while increasing the flexibility of its use in spite of differential signal supply.